Research News

Design and Test of Mixed-Signal Integrated Circuits

New methods for designing and testing mixed-signal Systems-On-Chip (SOC) are being developed by a team of faculty including Professors David Binkley , Rafic Makki , Chuck Stroud and Tom Weldon . The project is funded by DARPA's NEOCAD program (starting in July 2001 to June 2004) and supports 11 graduate students in the ECE department. The project entails the development of a new mixed-signal fault simulator, an automated approach to analog design optimization, Built-In-Self-Testing circuitry, and on-chip test sensors for developing high quality SOCs.

The project will result in a CAD tool package and design for test methods that will reduce the design cycle and improve the test efficiency of next-generation mixed-signal systems.

CMOS Integration of Low-Noise, Micropower, Front-End Electronics for a 100-Element Intracortical Electrode Array

Dr. Binkley 's research team is developing micropower, low-noise, analog CMOS integrated circuits for an intra-cortical neural probe that observe 100 neural signatures from a monkey's brain. These signals will be assessed to determine the neural request for limb movement. If successful, this research could lead to the development of neural controlled, human prosthetic limbs. This research is sponsored by NASA Jet Propulsion Laboratory (JPL).

Silicon-on-Insulator CMOS, Radiation Hardened, Low-Noise, Micropower Preamplifiers for NASA Deep Space Missions

Dr. Binkley 's research team is developing radiation hardened, low noise, micropower preamplifiers in silicon-on-insulator CMOS processes. A design methodology will be developed for design of these preamplifiers, which will allow for optimal low noise and micropower performance in the harsh environment of deep space. This research is sponsored by NASA Jet Propulsion Laboratory (JPL).

Device Materials/Processing Methodologies (Dr. Hasan)

A. Fabrication and characterization of power devices and radiation detectors based on wide bandgap materials, mainly SiC and group-III nitrides (AlN, GaN, InN). This project includes a new method for the fabrication of cubic 3C-SiC substrates. In this work, porous Si is used as a compliant singe crystalline seed for growth of 3C-SiC.  The growth then is conducted using an environmentally friendly non-toxic single gas source. Since 3C-SiC has only 0.6% lattice mismatch with AlN, it is one of the most suitable substrates for growth of group-III nitrides. The combination of this material system offers multitude of applications including high power, high frequency, high temperature, and light-emitting devices in addition to the advantage of integration with Si technology.

B. Solid-metal Mediated Molecular Beam Epitaxy (SMM-MBE): Recently, we have developed SMM-MBE a process that is both a dramatic technological advance, and a deeply interesting scientific phenomenon. In SMM-MBE, defect free single crystalline silicon is formed at a buried solid-metal/Si interface at low growth temperatures (T s < 400 o C). This process occurred during deposition from the vapor phase on the metal/Si heterostructure without measurable delay between deposition on the free metal surface and regrowth at the buried interface. The method combines epitaxial metallization and doping of Si in a single processing step. It has the potential for altering the current CMOS fabrication methods and can provide solutions to the challenges facing submicron device fabrication. Recently, we have used the method to grow SOI structures.

C. Development, characterization, and testing of a new family of cold cathode emitters based on group II-VI semiconductor and lanthanum monosulfide (a low work-function semimetallic compound). In theses devices, electrons are ballistically accelerated through a wide bandgap material into a low work-function surface layer, from which electrons are emitted into vacuum.      These emitters would be suitable as compact, efficient, low-voltage, high current cathodes for microwave tubes, electron beam lithography, and flat panel displays.

Next Generation Integrated Circuits

One of the major bottle necks of future generation high density ICs is efficient removal of heat.   Professors Ray Tsu and Dick Greene received a DARPA/ARO contract on the HERETIC Program (Heat Removal for Theomo-Integrated Circuits), starting 4/15/99 to 4/14/2002, in the amount of $1.838M, with the following subcontractors:   Sarnoff Corp.,State U of New York at Stony Brook, and NCSU.

Their program, entitled "Heat Removal by Inverse Nottingham Effect" involves removing the hot electrons by field emission into the vacuum via resonant tunneling, an innovation of Dr. Tsu while at IBM Research Center 15 years ago.   The replenishment of hot electrons removed by equilibrium cooler electrons results in cooling.

This research project opens a new avenue for realizing future high density ICs, particularly when these futuristic systems require non-planar circuits, commonly know as 3-D ICs.

Design for Test for Large Embedded SRAMs --- Click here for project website .

This project involves fault modeling, DFT, and on-chip current monitoring for testing large embedded memories. Emphasis is placed on physical verification of all test methods via actual chip fabrication and physical testing. The principal method used is iDDT testing which utilizes the dynamic power supply current to detect cell disturbs, opens and shorts.

This research program is funded by NSF and directed by Drs. Makki, Weldon and Stroud.